Nonvolatile memory ICs with higher densities are being introduced to the market daily. In order to achieve higher densities, IC manufacturers must continually decrease IC design rules (i.e., rules that state allowable dimensions of features used in the design and layout of integrated circuits). A smaller design rule relates directly to a reduced size of each cell of a memory array. With memory array cells already having deep submicron feature sizes, a slight change in processing of one memory cell relative to another during fabrication may result in a substantial difference in a behavior and characteristics of the cells with respect to one another.
Many conventional memory ICs operate in either a test mode in which input/output (I/O) pads are connected directly to an array of memory cells, or in a normal (or active) mode in which the I/O pads are connected through buffer circuitry to the array of memory cells. In the normal mode, the IC can perform read/write operations in which data are written to selected ones of the cells through an input buffer (or data are read from selected ones of the cells through an output buffer).
FIG. 1 is a simplified block diagram of a conventional prior art memory IC of this type. Although a thorough understanding of the conventional prior art memory IC presented herein is not required to appreciate embodiments of the present invention, it is nonetheless illustrative to fully appreciate the complexity and requirement of the present invention for testing memory cells.
A memory IC 103 of FIG. 1 includes at least one I/O pad 130 (for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit 110 for the I/O pad 130, a test mode switch 123, a plurality of address buffers A0 through Am for receiving memory address bits from an external device, a row decoder circuit (X-address decoder) 112, a column multiplexer circuit (Y-multiplexer) 114, a memory array 116 (comprising a plurality of columns of nonvolatile memory cells, such as a representative column 116A), a high voltage pad 109, a switch 121 connected between the high voltage pad 109 and other components of the memory IC 103, and a control unit 129. Each of address buffers A0 through Am includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym. The I/O buffer circuit 110 includes a write branch and a read branch. The write branch includes an input buffer 118. The read branch includes a sense amplifier 119 and output buffer 120.
In the normal operating mode of the memory IC 103 of FIG. 1, the control unit 129 can cause the memory IC 103 to execute a write operation in which it receives data (to be written to the memory array 116) from an external device at the I/O pad 130, buffers the data in the write branch, and then writes the data to the appropriate memory cell. Also in this normal operating mode, the control unit 129 can cause the memory IC 103 to execute a read operation in which it amplifies and buffers data (that has been read from array 116) in the read branch, and then asserts these data to the I/O pad 130.
Each of the cells (storage locations) of the memory array circuit 116 is indexed by a row index (an “X” index determined by the row decoder circuit 112) and a column index (a “Y” index output determined by the column multiplexer circuit 114). FIG. 2 is a simplified schematic diagram of columns of cells of the memory array 116 (with one column, e.g., the column on the right, corresponding to column 116A of FIG. 1). The column on the left side of FIG. 2 comprises “n” memory cells, each cell implemented by a floating-gate N-channel transistor N1, N2, . . . , N16. Each of the transistors N1-N16 is connected in series with each other between a bitline BL1, a bit select transistor on the bit select line, a global select transistor on the global select line GSL, and a source line potential. A gate for each of the floating-gate transistors is connected to a different wordline, WL1-WL16. The column on the right side of FIG. 2 in bitline 128, BL128, also comprises “n” memory cells, each cell implemented by one of floating-gate N-channel transistors Nn1, Nn2, . . . , Nn16. Each of the transistors in BL128 is connected similarly to the floating gate transistors, N1, N2, . . . , N16, of BL1.
Each memory cell is a nonvolatile memory cell since each of transistors N1, N2, . . . , N16, and Nn1, Nn2, . . . , Nn16 has a floating gate capable of a semi-permanent charge storage. The current drawn by each cell (i.e., by each of transistors N1, N2, . . . , N16, and Nn1, Nn2, . . . , Nn16) depends on an amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored semi-permanently in the corresponding cell. In cases in which each of transistors N1, N2, . . . , N16, and Nn1, Nn2, . . . , Nn16 is a flash memory device, the charge stored on the floating-gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source. Each of the floating-gate transistors has two threshold voltages, (1) a threshold voltage associated with a programmed condition (i.e., logic “0”); and (2) a threshold voltage associated with an erased condition (i.e., logic “1”). In each case, the threshold voltage approximately defines the gate potential needed to convert the device from “off” to “on.” Thus, a programmed cell can be “off” or “on” depending on the applied gate potential; and an erased cell can be “off” or “on” depending on the applied gate potential.
In response to address bits Y0-Ym, the column multiplexer circuit 114 (of FIG. 1) determines a column address which selects one of the columns of memory cells of the memory array 116 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address bits X0-Xn, the row decoder circuit 112 determines a row address which selects one cell in the selected column.
With continued reference to FIG. 1, the function of the switch 123 is to switch the memory IC 103 between its test mode and its normal operating mode. In the normal operating mode (i.e., with the switch 123 “off”), the memory IC 103 circuit executes a write operation as follows. Each of the address buffers A0 through An asserts one of the bits X0-Xn to the row decoder circuit 112, and each of the address buffers An+1 through An asserts one of the bits Y0-Ym to the column multiplexer circuit 114. In response to these address bits, the column multiplexer circuit 114 determines a column address (which selects one of the columns of memory cells of the memory array 116, such as the representative column 116A), and the row decoder circuit 112 determines a row address (which selects one cell in the selected column). In response to a write command supplied from the control unit 129, a signal (indicative of data) present at the output of the input buffer 118 (which has been enabled by the appropriate level of the control signal “DATA DRIVER ENABLE”) is asserted through the column multiplexer circuit 114 to a cell of the memory array 116 determined by the row and column address. During such a write operation, output buffer 120 is disabled (in response to an appropriate level of control signal OUTPUT ENABLE).
A data latch (not shown) is typically provided between the input buffer 118 and the I/O pad 130 for storing data (to be written to a memory cell) received from the I/O pad 130. When the latched data are sent to the input buffer 118, the input buffer 118 produces a voltage at Node 1 which is applied to the selected memory cell. The input buffer 118 is typically implemented as a tri-statable driver having an output which can be placed in a high impedance mode (and thus disabled) during a read operation. The input buffer 118 is disabled by asserting (to the input buffer 118) an appropriate level of the control signal DATA DRIVER ENABLE. In some implementations, the functions of the latch and the input buffer 118 are combined into a single device.
In the normal operating mode (with the switch 123 “off”), the FIG. 1 circuit executes a read operation as follows. Each of the address buffers A0-An asserts one of the bits X0-Xn to address the row decoder circuit 112, and each of the address buffers An-Am asserts one of the bits Y0-Ym to the column multiplexer circuit 114. In response to these address bits, the column multiplexer circuit 114 asserts a column address to the memory array 116 (which selects one of the columns of memory cells, such as the representative column 116A), and the row decoder circuit 112 asserts a row address to the memory array 116 (which selects one cell in the selected column). In response to a read command supplied from the control unit 129, a current signal indicative of a data value stored in the cell of array 116 (i.e., a data signal) determined by the row and column address is supplied through the bitline of the selected cell and then through the column multiplexer circuit 114 to the sense amplifier 119. This data signal is amplified in the sense amplifier 119, buffered in the output buffer 120 (which is enabled by an appropriate level of control signal “OUTPUT ENABLE”), and finally asserted at the I/O pad 130. During such a read operation, the input buffer 118 is disabled (in response to an appropriate level of control signal DATA DRIVER ENABLE).
The memory IC 103 of FIG. 1 also includes a high voltage pad 109 which receives a high voltage Vpp from an external circuit, such as a charge pump, and the switch 121 connected to the pad high voltage pad 109. During some steps of a typical erase or program sequence (in which the cells of the memory array 116 are erased or programmed), the control unit 129 sends a control signal to the switch 121, thereby causing the switch 121 to close, consequently asserting the high voltage Vpp to various components of the IC including the row decoder 112. Voltage Vpp is higher (e.g., typically Vpp=12 volts) than the normal operating mode supply voltage (e.g., VDD=5 volts or VDD=3.3 volts) for the MOS transistors of the memory IC 103.
When reading a selected cell of the memory array 116, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in the sense amplifier 119; if the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in the sense amplifier 119, as discussed supra. The sense amplifier 119 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary logic value of “0” or “1,” respectively) by comparing the voltage indicative of the cell state to a reference voltage. An outcome of this comparison is an output which is either high or low (corresponding to a digital value of “0” or “1”) which the sense amplifier 119 sends to the output buffer 120. The output buffer 120 in turn asserts a corresponding data signal to the I/O pad 130 (from which it can be accessed by an external device).
During a test mode, the input buffer 118, the sense amplifier 119, and the output buffer 120 are all disabled (in response to appropriate levels of their respective control signals DATA DRIVER ENABLE, SENSE AMPLIFIER ENABLE, and OUTPUT ENABLE, which are each generated by the control unit 129).
A complicated sequence of steps is necessary to perform an erase or program operation on the cells of a conventional nonvolatile memory IC as described since each of the individual cells typically behaves differently. Thus there is a need to ensure that all memory cells have at least a minimum margin at the end of each erase (or program) operation. This, however, does not mean that all the cells will be left with the same threshold voltage, Vth, at the end of an erase or program operation. For example, if during programming of all cells of an array, the minimum threshold voltage of all programmed cells is set to 3.3 volts, there may be many cells that have been programmed to a threshold voltage in a range from 5 to 5.5 volts at the end of the programming operation. So, there is a range of threshold voltages for the programmed cells. The same is true for an erase operation, and thus there is typically a range of threshold voltages for the erased cells.
Measuring a threshold voltage distribution of the cells of an array (after erase and program operations) is of great importance to memory manufacturers and designers. A degree of tightness of such a distribution is a good indicator of how well the memory elements have been processed (e.g., during fabrication of the IC).
One figure-of-merit, endurance, is the number of times that a memory cell (e.g., an EEPROM cell) can be erased and rewritten without corrupting data. An EEPROM cell will be cleared to a logic value of “1” (“off” cell) if charge is stored on the floating gate of the cell. The threshold voltage of a logic “1” cell is a positive voltage (e.g., typically approximately 2 to 3 volts). Read operations are relatively unlimited as they impose almost no stress on the cell. Therefore, endurance data apply only to program/erase cycles. Failure in a cell is defined as when a sense amplifier can no longer reliably differentiate logic state changes.
An EEPROM cell will be written to a logic “0” (“on” cell) if charge is cleared from the floating gate of the cell. The threshold voltage of a logic “0” cell is a negative voltage (e.g., typically approximately −1 to −2 volts). A margin voltage is measured to determine how well an EEPROM cell can be cleared and written. This margin voltage decreases with an increasing number of program/erase cycles. A margin “1” voltage is measured by applying a positive margin voltage to the sense gate of an EEPROM cell and raising the positive margin voltage until the “off” cell becomes an “on” cell. A positive margin voltage is input into a memory IC (such as the memory IC 103 of FIG. 1) by applying an external positive voltage through an I/O pad. In a similar way, it would be preferable to verify a margin “0” voltage which is measured by applying a negative margin voltage to the sense gate of the EEPROM cell and lowering the negative margin voltage until the “on” cell becomes an “off” cell. A program operation clears electrons from the floating gate. Therefore, a program threshold voltage, Vt, is low (i.e., a gate voltage, Vg, is negative with respect to a source voltage). Therefore, in order to test program operations, a negative threshold voltage is applied to the gate.
However, a typical electrostatic discharge (ESD) protection circuit on a test pad prohibits a negative voltage from being introduced. If a margin “0” voltage is less than approximately −0.6 volts, a p-n junction of the ESD circuit will be forward biased, potentially causing latchup. Therefore, usually only the positive margin voltage is tested and an assumption is made that the negative margin voltage will be symmetrically mirrored across the +0.5 voltage line (see FIG. 3). The theoretical program margin voltage of FIG. 3 indicates a threshold voltage of the erased cell, Vte, which will typically be a positive value, and an assumed threshold voltage of the programmed cell, Vtp, which will typically be a negative value. The difference between Vte and Vtp is the cell or program margin, Vpm, and is expressed asVpm=|Vtp−Vref|where Vref is an on chip reference voltage. Otherwise,Vpm≈|Vtp|when Vref=0 volts.
The program margin should be as large as practical since it makes it easier to distinguish a programmed cell from an erased cell. In other words, it makes it easier to read a data content of the cell. However, an assumption of program margin symmetry stated supra for an unmeasured threshold voltage of the programmed cell may be unjustified.
Therefore, what is needed is a method and circuit to provide a complete endurance cycle testing of both positive and negative margin voltages.